1. Field of the Invention
The present invention relates generally to PLL circuit apparatuses of an analog control system and phase difference detecting circuit apparatuses employed in the PLL circuit apparatuses and, more particularly, to a PLL circuit apparatus and a phase difference detecting circuit apparatus capable of controlling a gain of a loop filter at a high speed.
2. Description of the Background Art
Recently, with faster operation of semiconductor large scale integrated circuit devices (hereinafter referred to as LSIs), frequency of a reference clock signal to be a reference of the entirety of a system has drastically become a higher frequency. This reference clock signal is applied to each of the LSIs in the system and distributed to a plurality of loads by a driver in each LSI. However, since an operation speed of the drivers varies depending on the loads, a problem arises that a phase deviation of clock signals between the plurality of LSIs occurs. In order to solve this problem, it is considered that PLL circuits are each provided for all of the plurality of LSIs so as to synchronize phases of an input and an output of each driver.
FIG. 25 is a block diagram of a system in which PLL circuit apparatuses are distributed to respective LSIs in view of the above idea and shows the background of the invention.
With reference to FIG. 25, this system includes a CPU 200, a data bus 201, a reference clock signal line 11, and a plurality of LSIs 202-206 connected to the data bus 201 and the reference clock signal line 11. The CPU 200 transmits a data signal onto the data bus 201 and also transmits a reference clock signal onto the reference clock signal line 11 for making synchronization with each of the LSIs 202-206. Each of the LSIs 202-206 includes PLL circuits 207 and loads 208 and the like therein. In the following description, the reference characters of the signal lines are matched with those of signals for use.
In operation, a reference clock signal 11 transmitted from the CPU 200 is applied to each of the LSIs 202-206, and the PLL circuit 207 incorporated in each LSI generates an internal clock signal 12 which is synchronized in phase with the applied reference clock signal. By use of the internal clock signal thus generated, it is possible to solve the problem of a phase deviation due to the data bus in the system and the driver in each LSI.
FIG. 26 is a block diagram of a PLL circuit 207 of background art for use in the system of FIG. 25. The PLL circuit shown in FIG. 26 is an example of a PLL circuit of background art employing a voltage-controlled oscillator (hereinafter referred to as VCO) described in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 22, No. 2; Apr. 1987, pp. 255-261. With reference to FIG. 26, this PLL circuit apparatus includes a phase comparator 1, a charge pump circuit 2, a loop filter 3, a VCO 4 and an inverter (driver) 5. The phase comparator 1 compares a rising phase of a reference clock signal 11 to be a reference of phase synchronization and a rising phase of an internal clock signal 12 applied from the driver 5. When those rising phases are not in synchronization with each other, the phase comparator 1 outputs either an up signal 13 or a down signal 14. The charge pump circuit 2 receives the up signal 13 or the down signal 14 to output positive or negative charges in the form of pulses. The loop filter 3 smoothes an output of the charge pump circuit 2 and stores the smoothed output therein. This loop filter 3 includes resistors R1 and R2 and a capacitor C1. The gain of a loop is determined by those elements R1, R2 and C1. The VCO 4 changes an oscillation frequency in accordance with an output potential of the loop filter 3. The driver 5 generates an internal clock signal output from the VCO 4 in a desired duty ratio and applies the generated signal to a load in each LSI.
An operation of this PLL circuit apparatus will now be described with reference to FIGS. 27 and 28. FIGS. 27 and 28 are timing charts showing the operation of the PLL circuit apparatus shown in FIG. 26. FIG. 27 shows a case where the frequency of the internal clock signal is lower than that of the reference clock signal; and FIG. 28 shows a case where the frequency of the internal clock signal is higher than that of the reference clock signal. Referring to FIGS. 27 and 28, (a) represents the waveform of the internal clock signal; (b), the waveform of the reference clock signal; (c), the waveform of the up signal; (d), the waveform of the down signal; and (e), an output waveform of the loop filter 3.
First, in the case with FIG. 28, i.e., when the frequency of the internal clock signal is lower than that of the reference clock signal, the phase comparator 1 generates a pulse corresponding to a period of time from each rising of the reference clock signal to a rising of the internal clock signal immediately after the rising of the reference clock signal. This pulse is output onto the up signal line after a certain delay time (FIG. 28(c)). At the same time, the phase comparator 1 outputs a signal of a logic low level (or an "L" level) onto the down signal line (FIG. 28(d)). In response to this, the charge pump circuit 2 applies positive charges to the loop filter 3, however, because of a time constant of the resistors R1, R2 and the capacitor C1 of the loop filter 3, an output potential 18 of the loop filter 3 does not quickly rise but gradually rises by an integration operation (FIG. 28(e)). Consequently, the VCO 4 raises the oscillation frequency little by little, and hence, the phase of the internal clock signal becomes close to the phase of the reference clock signal. Similarly, in the case with FIG. 27, i.e., when the frequency of the internal clock signal is higher than that of the reference clock signal, the phase comparator 1 generates a pulse corresponding to a period of time from each rising of the internal clock signal to a rising of the reference clock signal immediately after the rising of the reference clock signal. This pulse is output onto the down signal line after a certain delay time. At the same time, the phase comparator 1 outputs a signal of a logic low level onto the up signal line. Accordingly, the charge pump circuit 2 applies negative charges to the loop filter 3, however, because of a time constant of the resistors R1 and R2 and the capacitor C1 of the loop filter 3, the output potential 18 of the loop filter 3 does not rise quickly but gradually falls by an integration operation. Consequently, the VCO 4 lowers the oscillation frequency little by little, and hence, the phase of the internal clock signal becomes close to the phase of the reference clock signal.
After the above operation, if both the phase and the frequency of the internal clock signal approximately match those of the reference clock signal, the amount of charges to be applied to the loop filter 3 by the charge pump circuit 2 becomes very small; however, because of the time constant of the loop filter 3, a slight amount of charges are integrated, so that the output potential 18 becomes almost constant. Thus, the VCO 4 keeps outputting clock signals provided when there is a match in phase and frequency, and the PLL circuit apparatus keeps maintaining the synchronization state of the reference clock signal and the internal clock signal.
Since the conventional PLL circuit apparatus of the analog system is thus structured, it is necessary to increase the time constant of the loop filter 3 so as to make the output of the loop filter 3 stable, in order to prevent a variation in the output of the VCO 4 in the state of phase synchronization. Thus, there is a problem that a period of time from time that the reference clock signal is applied to time that the phase of the internal clock signal is synchronized (synchronization pull-in time) becomes longer.
A PLL circuit apparatus for eliminating the above-described disadvantage is disclosed in Japanese Patent Laying-Open No. 62-199119.
FIG. 29 is a schematic block diagram of the PLL circuit apparatus shown in the above Patent Laying-Open. With reference to FIG. 29, this PLL circuit apparatus is different from one shown in FIG. 26 in that a loop filter 302 having two stages of loop gains is provided in place of the loop filter having one stage of loop gain and that a pull-in detector 301 is added. The loop filter 302 includes a switch circuit SW1 for setting the gain of the loop filter to be higher. The pull-in detector 301 serves to turn the switch circuit SW1 on to set the loop gain to be higher when a frequency difference between a reference clock signal 11 and an internal clock signal 12 is large, and it serves to turn the switch circuit SW1 off to set the loop gain to be lower after the frequency is pulled in. This enables a faster frequency pull-in.
FIG. 30 is a circuit diagram of the pull-in detector 301 shown in FIG. 29. With reference to FIG. 30 this pull-in detector 301 includes comparison circuits 401 and 402, NOR gates 403 and 404 and a counter 405.
In operation, the comparison circuits 401 and 402 compare an output voltage V.phi. which is in proportion to a phase difference from the charge pump circuit 2 with reference voltages Vr1 and Vr2 into which a supply voltage Vcc is divided by a resistance. When V.phi.&gt;Vr1, the comparison circuit 401 outputs "1". When V.phi.&lt;Vr2, the comparison circuit 402 outputs "1". When Vr1&gt;V.phi.&gt;Vr2, each of the comparison circuits 401 and 402 outputs "0". The NOR gate 403 outputs an output signal "0" when an output signal of the comparison circuit 401 or 402 is "1", while it outputs an output signal "1" when output signals of both the comparison circuits 401 and 402 are "0". The counter 405 is reset in response to the output signal "0" of the NOR gate 403 to output a gain control signal "0" for turning the switch circuit SW1 (FIG. 29) on. Further, the counter 405 responds to the output signal "1" of the NOR gate 403 to keep counting until pulses of the internal clock signal 12 input through the NOR gate 404 reach a predetermined number, and when the pulses reach the predetermined number, the counter 405 determines a pull-in state to output a gain control signal "1" for turning the switch circuit SW1 off.
Accordingly, the PLL circuit apparatus shown in FIGS. 29 and 30 sets the loop gain to be higher in the case with a higher frequency, and it maintains the loop gain to be higher until the output of the counter 405 attains "1" in the case with a nearly pull-in state. This enables shortening of the time required for the pull-in state.
However, since the PLL circuit apparatus shown in FIGS. 29 and 30 compares the analog output voltage V.phi. from the charge pump circuit 2 with the reference voltages Vr1 and Vr2, the voltages V.phi., Vr1 and Vr2 vary with a variation of the supply voltage. As a result, it is possible that a gain control signal for setting the loop gain to be higher despite the pull-in state is generated and that the loop gain is maintained to be lower despite a non pull-in state. That is, it is possible that malfunctions occur and the timing to generate the gain control signal is delayed.
Further, since detection of the pull-in state is made by counting the number of pulses of the internal clock signal by a predetermined number, there is a deviation from the actual pull-in state and there is a deviation between timing to generate the gain control signal for turning the switch circuit SW1 off and timing to stop that gain control signal.